A Reconfigurable Arbiter MPUF with High Resistance against Machine Learning Attack

Physical unclonable function (PUF) is an emerging hardware security primitive which is increasingly used to authenticate and identify Internet of Things (IoT) devices. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) provides new opportunities for novel PUFs due to inherent randomness sources, such as process variations, stochastic switching, and chaotic magnetization. In this article, we propose a hybrid STT-MRAM/complementary metal-oxide semiconductor (CMOS)-based reconfigurable arbiter PUF (MPUF) with enhanced performance metrics in terms of reliability, uniqueness, and uniformity. This design has a mean intra-hamming distance (HD) of 0.147%, a mean inter-HD of 50.21%, and passes the National Institute of Standards and Technology (NIST) statistical tests. The proposed arbiter MPUF features distinct advantages, such as reconfigurable architecture, challenge-dependent stage delays, and huge challenge-response pair (CRP) space. Moreover, the robustness of the proposed MPUF against machine learning (ML)-based modeling attacks is tested using three ML algorithms, namely support vector machine (SVM), linear regression (LR), and multilayer perceptron (MLP). Results show that the proposed reconfigurable arbiter MPUF is resistant to ML attacks and minimizes the ML attack prediction accuracy to less than 65.12% without XOR and less than 44.34% with XOR. Meanwhile, the correlation power analysis demonstrates that the proposed MPUF is also resilient to side-channel attacks.