A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits

For 45-nm technologies and below, the maximum operation frequency of integrated circuits (ICs) has reached multiple gigahertz. At the same time, the size of modern ICs has increased significantly with several billions of transistors integrated on each die. When a large number of transistors switch at the same time, high current consumption is generated. The high current consumption combining with the parasitic resistance and inductance of the power supply network generates a significant power supply noise peak, which causes abnormal reset and generates excessive radiation emission, and hence needs to be accurately monitored, adapted, and mitigated. This paper presents a novel power supply noise measurement and adaptation system that can monitor the peak power supply noise and make dynamic adaptation within one clock cycle. The proposed system has been implemented in Nangate 45-nm technology. It has been proved that the proposed measurement and the adaptation system can successfully avoid the performance degradation or functional failure due to excessive power supply noise. The peak power supply noise monitoring accuracy is 5 mV. The adaptation reaction time is 75%-100% of single system clock cycle. The proposed system is robust against temperature and process variation, and of negligible area overhead and power consumption.