TY - GEN
T1 - A Novel Dual Logic Locking Method to Prevent Counterfeit IP/IC
AU - Cui, Aobo
AU - Zhang, Dongrong
AU - Ren, Qiang
AU - Su, Donglin
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - With the popularization of horizontal business model in the semiconductor design and manufacturing industry, IC piracy frequently occurs in the supply chain by overpro-ducing and transporting unqualified/defective devices, reverse engineering, etc. This paper proposes a dual logic locking (DLL) method to prevent counterfeit IP/IC. Based on this method, the foundry/assembly can perform tests in the state of IP/IC output obfuscated and obtain test results. Then, the designer decides whether to permanently activate the IP/IC based on the encrypted test results. The proposed method only needs one data exchange between the designer and foundry/assembly compared with the secure split test method. The proposed DLL was implemented on several benchmarks, and the experimental result shows that it has a low overhead. In addition, the security analysis shows that it is robust against IP/IC piracies.
AB - With the popularization of horizontal business model in the semiconductor design and manufacturing industry, IC piracy frequently occurs in the supply chain by overpro-ducing and transporting unqualified/defective devices, reverse engineering, etc. This paper proposes a dual logic locking (DLL) method to prevent counterfeit IP/IC. Based on this method, the foundry/assembly can perform tests in the state of IP/IC output obfuscated and obtain test results. Then, the designer decides whether to permanently activate the IP/IC based on the encrypted test results. The proposed method only needs one data exchange between the designer and foundry/assembly compared with the secure split test method. The proposed DLL was implemented on several benchmarks, and the experimental result shows that it has a low overhead. In addition, the security analysis shows that it is robust against IP/IC piracies.
KW - Counterfeit
KW - IP/IC piracy
KW - Logic Locking
KW - Supply Chain Secu-rity
UR - https://www.scopus.com/pages/publications/85143173756
U2 - 10.1109/ITCAsia55616.2022.00024
DO - 10.1109/ITCAsia55616.2022.00024
M3 - 会议稿件
AN - SCOPUS:85143173756
T3 - Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022
SP - 79
EP - 84
BT - Proceedings - 2022 IEEE International Test Conference in Asia, ITC-Asia 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th IEEE International Test Conference in Asia, ITC-Asia 2022
Y2 - 24 August 2022 through 26 August 2022
ER -