A multi-level collaboration low-power design based on embedded system

Xiang Wang; Lin Li; Longbin Zhang; Weike Wang; Rong Zhang; Yi Zhang; Quanneng Shen

doi:10.1109/SOCC.2015.7406937

A multi-level collaboration low-power design based on embedded system

Xiang Wang
, Lin Li
, Longbin Zhang
, Weike Wang
, Rong Zhang
, Yi Zhang
, Quanneng Shen

School of Electronic and Information Engineering

Beihang University
CAS - Institute of Computing Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This essay provides a multi-level collaboration low-power design based on embedded processor, builds SoC (System-on-Chip) and designs a low-power SoC by register level, system level and gate level. The designed clock gating module, power management module and system program coordination can be used to realize the sleep and wake up functions on SoC. In order to realize a multi-level collaboration low-power designing, gating clock circuit can be used in circuit designing.

Original language	English
Title of host publication	Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015
Editors	Thomas Buchner, Danella Zhao, Karan Bhatia, Ramalingam Sridhar
Publisher	IEEE Computer Society
Pages	186-190
Number of pages	5
ISBN (Electronic)	9781467390934
DOIs	https://doi.org/10.1109/SOCC.2015.7406937
State	Published - 12 Feb 2016
Event	28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China Duration: 8 Sep 2015 → 11 Sep 2015

Publication series

Name	International System on Chip Conference
Volume	2016-February
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	28th IEEE International System on Chip Conference, SOCC 2015
Country/Territory	China
City	Beijing
Period	8/09/15 → 11/09/15

Keywords

clock gating
dynamic power manager
low-power
multi-level

Access to Document

10.1109/SOCC.2015.7406937

Cite this

Wang, X., Li, L., Zhang, L., Wang, W., Zhang, R., Zhang, Y., & Shen, Q. (2016). A multi-level collaboration low-power design based on embedded system. In T. Buchner, D. Zhao, K. Bhatia, & R. Sridhar (Eds.), Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015 (pp. 186-190). Article 7406937 (International System on Chip Conference; Vol. 2016-February). IEEE Computer Society. https://doi.org/10.1109/SOCC.2015.7406937

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title = "A multi-level collaboration low-power design based on embedded system",

abstract = "This essay provides a multi-level collaboration low-power design based on embedded processor, builds SoC (System-on-Chip) and designs a low-power SoC by register level, system level and gate level. The designed clock gating module, power management module and system program coordination can be used to realize the sleep and wake up functions on SoC. In order to realize a multi-level collaboration low-power designing, gating clock circuit can be used in circuit designing.",

keywords = "clock gating, dynamic power manager, low-power, multi-level",

author = "Xiang Wang and Lin Li and Longbin Zhang and Weike Wang and Rong Zhang and Yi Zhang and Quanneng Shen",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 28th IEEE International System on Chip Conference, SOCC 2015 ; Conference date: 08-09-2015 Through 11-09-2015",

year = "2016",

month = feb,

day = "12",

doi = "10.1109/SOCC.2015.7406937",

language = "英语",

series = "International System on Chip Conference",

publisher = "IEEE Computer Society",

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Wang, X, Li, L, Zhang, L, Wang, W, Zhang, R, Zhang, Y & Shen, Q 2016, A multi-level collaboration low-power design based on embedded system. in T Buchner, D Zhao, K Bhatia & R Sridhar (eds), Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015., 7406937, International System on Chip Conference, vol. 2016-February, IEEE Computer Society, pp. 186-190, 28th IEEE International System on Chip Conference, SOCC 2015, Beijing, China, 8/09/15. https://doi.org/10.1109/SOCC.2015.7406937

A multi-level collaboration low-power design based on embedded system. / Wang, Xiang; Li, Lin; Zhang, Longbin et al.
Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. ed. / Thomas Buchner; Danella Zhao; Karan Bhatia; Ramalingam Sridhar. IEEE Computer Society, 2016. p. 186-190 7406937 (International System on Chip Conference; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Li, Lin

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AU - Wang, Weike

AU - Zhang, Rong

AU - Zhang, Yi

AU - Shen, Quanneng

PY - 2016/2/12

Y1 - 2016/2/12

N2 - This essay provides a multi-level collaboration low-power design based on embedded processor, builds SoC (System-on-Chip) and designs a low-power SoC by register level, system level and gate level. The designed clock gating module, power management module and system program coordination can be used to realize the sleep and wake up functions on SoC. In order to realize a multi-level collaboration low-power designing, gating clock circuit can be used in circuit designing.

AB - This essay provides a multi-level collaboration low-power design based on embedded processor, builds SoC (System-on-Chip) and designs a low-power SoC by register level, system level and gate level. The designed clock gating module, power management module and system program coordination can be used to realize the sleep and wake up functions on SoC. In order to realize a multi-level collaboration low-power designing, gating clock circuit can be used in circuit designing.

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KW - dynamic power manager

KW - low-power

KW - multi-level

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DO - 10.1109/SOCC.2015.7406937

M3 - 会议稿件

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PB - IEEE Computer Society

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ER -

Wang X, Li L, Zhang L, Wang W, Zhang R, Zhang Y et al. A multi-level collaboration low-power design based on embedded system. In Buchner T, Zhao D, Bhatia K, Sridhar R, editors, Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015. IEEE Computer Society. 2016. p. 186-190. 7406937. (International System on Chip Conference). doi: 10.1109/SOCC.2015.7406937

A multi-level collaboration low-power design based on embedded system

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