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A Gb/s parallel block-based Viterbi decoder for convolutional codes on GPU

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we propose a parallel block-based Viterbi decoder (PBVD) on the graphic processing unit (GPU) platform for the decoding of convolutional codes. The decoding procedure is simplified and parallelized, and the characteristic of the trellis is exploited to reduce the metric computation. Based on the compute unified device architecture (CUDA), two kernels with different parallelism are designed to map two decoding phases. Moreover, the optimal design of data structures for several kinds of intermediate information are presented, to improve the efficiency of internal memory transactions. Experimental results demonstrate that the proposed decoder achieves high throughput of 598Mbps on NVIDIA GTX580 and 1802Mbps on GTX980 for the 64-state convolutional code, which are 1.5 times speedup compared to the existing fastest works on GPUs.

Original languageEnglish
Title of host publication2016 8th International Conference on Wireless Communications and Signal Processing, WCSP 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509028603
DOIs
StatePublished - 21 Nov 2016
Event8th International Conference on Wireless Communications and Signal Processing, WCSP 2016 - Yangzhou, China
Duration: 13 Oct 201615 Oct 2016

Publication series

Name2016 8th International Conference on Wireless Communications and Signal Processing, WCSP 2016

Conference

Conference8th International Conference on Wireless Communications and Signal Processing, WCSP 2016
Country/TerritoryChina
CityYangzhou
Period13/10/1615/10/16

Keywords

  • CUDA
  • SDR
  • Viterbi algorithm
  • convolutional codes
  • parallel decoding

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