Skip to main navigation Skip to search Skip to main content

A flexible FPGA-based video compression system and its testing interface

  • Rui Wang*
  • , Hongxu Jiang
  • , Qiujie Li
  • , Bo Li
  • , Yifang Zen
  • *Corresponding author for this work
  • Beihang University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a FPGA-based Video Compression System (FVCS) and its Testing Interface System (TIS). The FVCS is designed in order to implement complex algorithms such as MPEG-4. TIS is implemented to facilitate functions' development. A High-end FPGA from Xilinx's Vertex-4 series has been used to perform the functions including video acquisition, compression and bit-stream transmission. FVCS implements an open architecture with a separate video lens module and can connect an optional extend memory system. Two compression solutions based on FVCS's architecture demonstrate the flexibility.

Original languageEnglish
Title of host publication8th International Conference on Signal Processing, ICSP 2006
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)0780397371, 9780780397378
DOIs
StatePublished - 2006
Event8th International Conference on Signal Processing, ICSP 2006 - Guilin, China
Duration: 16 Nov 200620 Nov 2006

Publication series

NameInternational Conference on Signal Processing Proceedings, ICSP
Volume1

Conference

Conference8th International Conference on Signal Processing, ICSP 2006
Country/TerritoryChina
CityGuilin
Period16/11/0620/11/06

Keywords

  • FPGA video compression embedded

Fingerprint

Dive into the research topics of 'A flexible FPGA-based video compression system and its testing interface'. Together they form a unique fingerprint.

Cite this