A Fault-Tolerant Die-to-Die Interconnect with Retry and Repair Mechanisms for Chiplet-Based Systems

With the slowdown of Moore's Law, chiplet-based integration has emerged as a promising strategy for improving system performance and yield in the post-Moore era. The die-todie (D2D) interconnect serves as the critical interface enabling communication among chiplets. However, the use of dense microbump arrays and advanced packaging technologies increase the risk of contact failures, thereby posing significant challenges to system reliability. This paper presents a lightweight and faulttolerant D2D interconnect that integrates a retry mechanism with a link repair scheme to ensure data integrity and maintain system availability. Implemented in Verilog and validated on a Xilinx XCVU440 FPGA, the proposed D2D interconnect achieves 14.76 Gb/s throughput and a 37.5% reduction in hardware resource utilization compared with a previously reported low-cost chip-to-chip interconnect.