A Custom RISC-V ISA with Scalable Processing Units for Efficient Neural Network Inference

A customized RISC-V ISA with integrated digital accelerators offers a promising solution to improve energy efficiency in neural network inference. However, it often requires multiple instructions per accelerator operation, which limits computational efficiency during deep neural network inference. To overcome the instruction overhead, this design introduces a dedicated instruction set that enables scalable and fine-grained accelerator control. By incorporating the pattern-driven instruction mode, this design exploits the neural layer regularity to support efficient instruction iteration. Furthermore, this digital accelerator leverages hardware reuse for logic operations, forming a fusion-style architecture that integrates reconfigurable components. Experimental results demonstrate that the custom RISC-V ISA achieves an average runtime speedup of 8.26× and reduces the instruction count by 14.71×. This design also yields an average 8.73× reduction in cycles per instruction across MobileNetV2, ResNet50, VGG19, EfficientNet, and DenseNet-BC, validating its effectiveness across representative benchmarks. Additionally, it improves average energy efficiency by 1.74×, outperforming state-of-the-art designs.