A conflict-free approach for parallelizing SAT-based de-camouflaging attacks

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Abstract

As one of the most effective proactive countermeasures against reverse engineering, circuit camouflaging has emerged to be a hot research topic and it is becoming a mature technology with the development of various de-camouflaging attacks. Among them, the SAT-based method is the most powerful one to defeat circuit camouflaging. However, SAT-based attacks have scalability problem due to the complexity of the underlying SAT solvers, and straightforward approach to parallelize SAT-based attacks will fail. In this paper, we propose a two-level partition method (independent module partitioning and k-medoids clustering), together with a novel conflict avoidance strategy to solve the problem. Experimental results on OpenSparc T1 microprocessor controller demonstrate that our approach can on average reduce the scales of the SAT formulas by more than 50% and achieve 3.6x speedup on the best-known SAT-based de-camouflaging tool.

Original languageEnglish
Title of host publicationASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages259-264
Number of pages6
ISBN (Electronic)9781509006021
DOIs
StatePublished - 20 Feb 2018
Externally publishedYes
Event23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
Duration: 22 Jan 201825 Jan 2018

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2018-January

Conference

Conference23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Country/TerritoryKorea, Republic of
CityJeju
Period22/01/1825/01/18

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