A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

Kaili Zhang; Zhongzhen Tong; Xinxin Liang; Chengzhi Wang; You Wang; Yue Zhang; Weisheng Zhao; Lang Zeng; Deming Zhang

doi:10.1109/TCSII.2023.3322556

A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

Kaili Zhang
, Zhongzhen Tong
, Xinxin Liang
, Chengzhi Wang
, You Wang
, Yue Zhang
, Weisheng Zhao
, Lang Zeng^*
, Deming Zhang^*

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

Beihang University
Academy of Military Medical Science China
Nanjing University of Aeronautics and Astronautics

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.

Original language	English
Pages (from-to)	1077-1081
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	71
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2023.3322556
State	Published - 1 Mar 2024

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Charge-domain
cell-embedded DA conversion
compute-in-memory (CIM)
two-stage AD conversion

Access to Document

10.1109/TCSII.2023.3322556

Cite this

@article{e63909046794479e8aa2709a5bf9401b,

title = "A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation",

abstract = "A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.",

keywords = "Charge-domain, cell-embedded DA conversion, compute-in-memory (CIM), two-stage AD conversion",

author = "Kaili Zhang and Zhongzhen Tong and Xinxin Liang and Chengzhi Wang and You Wang and Yue Zhang and Weisheng Zhao and Lang Zeng and Deming Zhang",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2024",

month = mar,

day = "1",

doi = "10.1109/TCSII.2023.3322556",

language = "英语",

volume = "71",

pages = "1077--1081",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

AU - Zhang, Kaili

AU - Tong, Zhongzhen

AU - Liang, Xinxin

AU - Wang, Chengzhi

AU - Wang, You

AU - Zhang, Yue

AU - Zhao, Weisheng

AU - Zeng, Lang

AU - Zhang, Deming

PY - 2024/3/1

Y1 - 2024/3/1

N2 - A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.

AB - A charge-domain compute-in-memory (CIM) macro is proposed to implement bit-scalable multiply-and-accumulate (MAC) operation with the cell-embedded digital-to-analog (DA) conversion and two-stage analog-to-digital (AD) conversion. The cell-embedded DA conversion is achieved among the capacitances inside the proposed 12T2C SRAM CIM cell, enabling 1-4 bit input. Then, multiple columns of CIM macro are merged to form 1/2/4 bit weight by controlling the switches in the multi-bit weight switch array. The proposed two-stage AD conversion circuit for 4-b output can reduce the output cycles with high energy efficiency. By using the CMOS 55nm design kit, the simulation results show that a 4kb CIM macro can achieve a throughput of 151.70-1260.31 GOPS and energy efficiency of 97.99-419.55 TOPS/W.

KW - Charge-domain

KW - cell-embedded DA conversion

KW - compute-in-memory (CIM)

KW - two-stage AD conversion

UR - https://www.scopus.com/pages/publications/85174834160

U2 - 10.1109/TCSII.2023.3322556

DO - 10.1109/TCSII.2023.3322556

M3 - 文章

AN - SCOPUS:85174834160

SN - 1549-7747

VL - 71

SP - 1077

EP - 1081

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 3

ER -

A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation

Abstract

UN SDGs

Keywords

Access to Document

Other files and links

Fingerprint

Cite this