Abstract
This work presents a 2-MS/s 18-bit successive-approximation-register analog-to-digital converter (ADC). Acapacitor digital-to-analog converter (CDAC) and a resistor digital-to-analog converter (RDAC) are cascaded to avoid the linearity limitation caused by parasitic capacitors on the bridge capacitor between the CDAC and the RDAC. An optimal-combination-algorithm (OCA)-based calibration is adopted to improve the linearity of the CDAC and the matching between CDAC and the bridge capacitor, and a least significant bit (LSB)-side dynamic element matching (DEM) strategy is applied to further improve the CDAC linearity. As for the RDAC, this work makes it calibration free by combining the parallel R-unit and R-2R topology. Measurement results show that the proposed ADC can achieve 91.4-dB signal-to-noise and distortion ratio (SNDR), 12.0-parts-per-million (ppm) (3.1-LSB) integral non-linearity (INL), and 174.0-dB FOMS,SNDR (including the power consumed by the calibration logic), and the worst-case INL across 25 dies improves from 72.5ppm (19.0LSB) to 18.8ppm (4.9LSB) after the OCA-based calibration and theLSB-side DEM. To the best of the authors' knowledge, this is the first high-precision (resolution ≥ 16 bit) data converter adopting OCA-based calibration.
| Original language | English |
|---|---|
| Journal | IEEE Transactions on Circuits and Systems |
| DOIs | |
| State | Accepted/In press - 2026 |
Keywords
- calibration
- capacitor digital-to-analog converter (CDAC)
- LSB-side DEM
- maximal linearly independent subset
- optimal combination algorithm
- resistor digital-to-analog converter (RDAC)
- Successive-approximation-register (SAR) analog-to-digital converter (ADC)
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