TY - GEN
T1 - A 6.86Tb/s Bandwidth SOT-MRAM Sensing Scheme with Configurable Full-Column Over Frequency Technique for Near Memory Computing
AU - Jiang, Xinpeng
AU - Chen, Hanting
AU - Wang, Zhaohao
AU - Zhang, He
AU - Zhao, Weisheng
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026
Y1 - 2026
N2 - The proliferation of multimodal systems, which heavily rely on efficient visual backbone networks like Convolutional Neural Networks (CNNs), is driving the adoption of Computing-in-Memory (CIM) architectures for edge deployment. Magnetoresistive RAM (MRAM) is an attractive weight storage medium for such systems due to its non-volatility, inherent radiation hardness, and high-speed read/write potential. However, the computational performance of digital MRAM-CIM chips is bottlenecked by the MRAM read bandwidth, thereby precluding full utilization of its non-volatility and limiting overall energy efficiency, especially as network depth scales. To this end, we introduce a compact, dual-path-optimized full-column-readout sense amplifier (SA) for reliable reading, complemented by a stage-aware over-frequency scheme with algorithm retraining to preserve inferency accuracy. Simulation results of our Spin-Orbit-Torque (SOT)-MRAM design in a 32-channel CIM architecture show a bandwidth of 6.86 Tb/s and a read energy efficiency of 34.5 fJ/bit. This represents a 33.9× improvement in normalized bandwidth over previous cutting-edge designs.
AB - The proliferation of multimodal systems, which heavily rely on efficient visual backbone networks like Convolutional Neural Networks (CNNs), is driving the adoption of Computing-in-Memory (CIM) architectures for edge deployment. Magnetoresistive RAM (MRAM) is an attractive weight storage medium for such systems due to its non-volatility, inherent radiation hardness, and high-speed read/write potential. However, the computational performance of digital MRAM-CIM chips is bottlenecked by the MRAM read bandwidth, thereby precluding full utilization of its non-volatility and limiting overall energy efficiency, especially as network depth scales. To this end, we introduce a compact, dual-path-optimized full-column-readout sense amplifier (SA) for reliable reading, complemented by a stage-aware over-frequency scheme with algorithm retraining to preserve inferency accuracy. Simulation results of our Spin-Orbit-Torque (SOT)-MRAM design in a 32-channel CIM architecture show a bandwidth of 6.86 Tb/s and a read energy efficiency of 34.5 fJ/bit. This represents a 33.9× improvement in normalized bandwidth over previous cutting-edge designs.
KW - AI inference
KW - CIM
KW - circuit simulation and optimization
KW - high band-width
KW - SOT-MRAM
UR - https://www.scopus.com/pages/publications/105043455053
U2 - 10.1109/ISCAS66217.2026.11562230
DO - 10.1109/ISCAS66217.2026.11562230
M3 - 会议稿件
AN - SCOPUS:105043455053
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2118
EP - 2122
BT - ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026
Y2 - 24 May 2026 through 27 May 2026
ER -