A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation

Junda Zhao; Yimo Du; Taoyi Wang; Liang Zhang; Junzhan Liu; He Zhang; Wang Kang

doi:10.1109/ISCAS66217.2026.11562847

A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation

Junda Zhao
, Yimo Du
, Taoyi Wang
, Liang Zhang
, Junzhan Liu^*
, He Zhang^*
, Wang Kang^*

^*Corresponding author for this work

School of Integrated Circuit Science and Engineering

Beihang University
Primevision Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The growing integration of artificial intelligence in edge applications has intensified demands for high-frame-rate, low-power vision sensors, challenging conventional visual systems that separate sensing, computation and storage - an architecture limited by data movement bottlenecks which can be mitigated by sensing with computing. This work introduces a fully parallel convolutional digital pixel sensor (FPC-DPS) architecture employing a subthreshold self-ramped single-slope ADC (S³S-ADC) with self-calibrating current registers. By integrating a global nine-direction propagation PWM (G9DP-PWM) and a relaxation oscillator-based global clock pulse frequency modulation (GC-PFM) strategy, the design seamlessly merges sensing, analog-to-digital conversion, and convolution at pixel level, achieving fully parallel in-sensor computing (ISC). Simulations demonstrate dual-mode operation with 100,000 FPS in imaging mode and 30,000 FPS in convolution mode using 4b signed weights and 8b quantization, attaining 5.74 TOPS/W in energy efficiency and an iFoM of 1.54 pJ/pix•fps, offering an efficient solution for next-generation edge AI visual systems.

Original language	English
Title of host publication	ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	3481-3485
Number of pages	5
ISBN (Electronic)	9798331577698
DOIs	https://doi.org/10.1109/ISCAS66217.2026.11562847
State	Published - 2026
Event	2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026 - Shanghai, China Duration: 24 May 2026 → 27 May 2026

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026
Country/Territory	China
City	Shanghai
Period	24/05/26 → 27/05/26

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

artificial intelligence (AI)
cmos image sensor (CIS)
convolutional neural network (CNN)
fully parallel
high frame rate (HFR)
in-sensor computing (ISC)

Access to Document

10.1109/ISCAS66217.2026.11562847

Cite this

Zhao, J., Du, Y., Wang, T., Zhang, L., Liu, J., Zhang, H., & Kang, W. (2026). A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation. In ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems (pp. 3481-3485). (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS66217.2026.11562847

Zhao, Junda ; Du, Yimo ; Wang, Taoyi et al. / A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation. ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2026. pp. 3481-3485 (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{82194171803d4b669d0846126c63ad6f,

title = "A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation",

abstract = "The growing integration of artificial intelligence in edge applications has intensified demands for high-frame-rate, low-power vision sensors, challenging conventional visual systems that separate sensing, computation and storage - an architecture limited by data movement bottlenecks which can be mitigated by sensing with computing. This work introduces a fully parallel convolutional digital pixel sensor (FPC-DPS) architecture employing a subthreshold self-ramped single-slope ADC (S3S-ADC) with self-calibrating current registers. By integrating a global nine-direction propagation PWM (G9DP-PWM) and a relaxation oscillator-based global clock pulse frequency modulation (GC-PFM) strategy, the design seamlessly merges sensing, analog-to-digital conversion, and convolution at pixel level, achieving fully parallel in-sensor computing (ISC). Simulations demonstrate dual-mode operation with 100,000 FPS in imaging mode and 30,000 FPS in convolution mode using 4b signed weights and 8b quantization, attaining 5.74 TOPS/W in energy efficiency and an iFoM of 1.54 pJ/pix•fps, offering an efficient solution for next-generation edge AI visual systems.",

keywords = "artificial intelligence (AI), cmos image sensor (CIS), convolutional neural network (CNN), fully parallel, high frame rate (HFR), in-sensor computing (ISC)",

author = "Junda Zhao and Yimo Du and Taoyi Wang and Liang Zhang and Junzhan Liu and He Zhang and Wang Kang",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026 ; Conference date: 24-05-2026 Through 27-05-2026",

year = "2026",

doi = "10.1109/ISCAS66217.2026.11562847",

language = "英语",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "3481--3485",

booktitle = "ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems",

address = "美国",

}

Zhao, J, Du, Y, Wang, T, Zhang, L, Liu, J, Zhang, H & Kang, W 2026, A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation. in ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 3481-3485, 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026, Shanghai, China, 24/05/26. https://doi.org/10.1109/ISCAS66217.2026.11562847

A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation. / Zhao, Junda; Du, Yimo; Wang, Taoyi et al.
ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2026. p. 3481-3485 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation

AU - Zhao, Junda

AU - Du, Yimo

AU - Wang, Taoyi

AU - Zhang, Liang

AU - Liu, Junzhan

AU - Zhang, He

AU - Kang, Wang

PY - 2026

Y1 - 2026

N2 - The growing integration of artificial intelligence in edge applications has intensified demands for high-frame-rate, low-power vision sensors, challenging conventional visual systems that separate sensing, computation and storage - an architecture limited by data movement bottlenecks which can be mitigated by sensing with computing. This work introduces a fully parallel convolutional digital pixel sensor (FPC-DPS) architecture employing a subthreshold self-ramped single-slope ADC (S3S-ADC) with self-calibrating current registers. By integrating a global nine-direction propagation PWM (G9DP-PWM) and a relaxation oscillator-based global clock pulse frequency modulation (GC-PFM) strategy, the design seamlessly merges sensing, analog-to-digital conversion, and convolution at pixel level, achieving fully parallel in-sensor computing (ISC). Simulations demonstrate dual-mode operation with 100,000 FPS in imaging mode and 30,000 FPS in convolution mode using 4b signed weights and 8b quantization, attaining 5.74 TOPS/W in energy efficiency and an iFoM of 1.54 pJ/pix•fps, offering an efficient solution for next-generation edge AI visual systems.

AB - The growing integration of artificial intelligence in edge applications has intensified demands for high-frame-rate, low-power vision sensors, challenging conventional visual systems that separate sensing, computation and storage - an architecture limited by data movement bottlenecks which can be mitigated by sensing with computing. This work introduces a fully parallel convolutional digital pixel sensor (FPC-DPS) architecture employing a subthreshold self-ramped single-slope ADC (S3S-ADC) with self-calibrating current registers. By integrating a global nine-direction propagation PWM (G9DP-PWM) and a relaxation oscillator-based global clock pulse frequency modulation (GC-PFM) strategy, the design seamlessly merges sensing, analog-to-digital conversion, and convolution at pixel level, achieving fully parallel in-sensor computing (ISC). Simulations demonstrate dual-mode operation with 100,000 FPS in imaging mode and 30,000 FPS in convolution mode using 4b signed weights and 8b quantization, attaining 5.74 TOPS/W in energy efficiency and an iFoM of 1.54 pJ/pix•fps, offering an efficient solution for next-generation edge AI visual systems.

KW - artificial intelligence (AI)

KW - cmos image sensor (CIS)

KW - convolutional neural network (CNN)

KW - fully parallel

KW - high frame rate (HFR)

KW - in-sensor computing (ISC)

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DO - 10.1109/ISCAS66217.2026.11562847

M3 - 会议稿件

AN - SCOPUS:105043429015

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 3481

EP - 3485

BT - ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026

Y2 - 24 May 2026 through 27 May 2026

ER -

Zhao J, Du Y, Wang T, Zhang L, Liu J, Zhang H et al. A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation. In ISCAS 2026 - 2026 IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2026. p. 3481-3485. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS66217.2026.11562847

A 4/8b High-Precision Fully-Parallel In-Sensor Computing Chip with Subthreshold Digital Pixel and Hybrid Pulse Modulation

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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