A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain

Lianbo Wu; Thomas Burger; Philipp Schonle; Qiuting Huang

doi:10.1109/VLSICircuits18222.2020.9162777

A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain

Lianbo Wu
, Thomas Burger
, Philipp Schonle
, Qiuting Huang

Swiss Federal Institute of Technology Zurich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper presents a Fractional-N (Frac-N) digital phase-locked loop (DPLL) that resolves phase error (PE) in fully differential voltage (FDV) domain, where power-efficient PE detection can be accomplished with higher CMRR, lower PVT sensitivity, finer resolution and better linearity as compared to gate delay-dependent time domain. The implemented DPLL covers the frac-N operation by a 10b DAC in voltage domain (V-domain). A differential dv/dt ramp is employed to linearly transfer the frac-N phase difference into a small range voltage error, which is digitized by a narrow range but fine resolution 7b ADC. The DPLL achieves an integrated RMS jitter of 101fs with -56dBc worst-case fractional spur and consumes 9.2mW which translates to a FoM of -250.3dB.

Original language	English
Title of host publication	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728199429
DOIs	https://doi.org/10.1109/VLSICircuits18222.2020.9162777
State	Published - Jun 2020
Externally published	Yes
Event	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, United States Duration: 16 Jun 2020 → 19 Jun 2020

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2020-June

Conference

Conference	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Country/Territory	United States
City	Honolulu
Period	16/06/20 → 19/06/20

Access to Document

10.1109/VLSICircuits18222.2020.9162777

Cite this

Wu, L., Burger, T., Schonle, P., & Huang, Q. (2020). A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings Article 9162777 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2020-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSICircuits18222.2020.9162777

Wu, Lianbo ; Burger, Thomas ; Schonle, Philipp et al. / A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain. 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{481da2b62f684c17a483c84c0efaca5b,

title = "A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain",

abstract = "This paper presents a Fractional-N (Frac-N) digital phase-locked loop (DPLL) that resolves phase error (PE) in fully differential voltage (FDV) domain, where power-efficient PE detection can be accomplished with higher CMRR, lower PVT sensitivity, finer resolution and better linearity as compared to gate delay-dependent time domain. The implemented DPLL covers the frac-N operation by a 10b DAC in voltage domain (V-domain). A differential dv/dt ramp is employed to linearly transfer the frac-N phase difference into a small range voltage error, which is digitized by a narrow range but fine resolution 7b ADC. The DPLL achieves an integrated RMS jitter of 101fs with -56dBc worst-case fractional spur and consumes 9.2mW which translates to a FoM of -250.3dB.",

author = "Lianbo Wu and Thomas Burger and Philipp Schonle and Qiuting Huang",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 ; Conference date: 16-06-2020 Through 19-06-2020",

year = "2020",

month = jun,

doi = "10.1109/VLSICircuits18222.2020.9162777",

language = "英语",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings",

address = "美国",

}

Wu, L, Burger, T, Schonle, P & Huang, Q 2020, A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain. in 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings., 9162777, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2020-June, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, United States, 16/06/20. https://doi.org/10.1109/VLSICircuits18222.2020.9162777

A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain. / Wu, Lianbo; Burger, Thomas; Schonle, Philipp et al.
2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9162777 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2020-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain

AU - Wu, Lianbo

AU - Burger, Thomas

AU - Schonle, Philipp

AU - Huang, Qiuting

PY - 2020/6

Y1 - 2020/6

N2 - This paper presents a Fractional-N (Frac-N) digital phase-locked loop (DPLL) that resolves phase error (PE) in fully differential voltage (FDV) domain, where power-efficient PE detection can be accomplished with higher CMRR, lower PVT sensitivity, finer resolution and better linearity as compared to gate delay-dependent time domain. The implemented DPLL covers the frac-N operation by a 10b DAC in voltage domain (V-domain). A differential dv/dt ramp is employed to linearly transfer the frac-N phase difference into a small range voltage error, which is digitized by a narrow range but fine resolution 7b ADC. The DPLL achieves an integrated RMS jitter of 101fs with -56dBc worst-case fractional spur and consumes 9.2mW which translates to a FoM of -250.3dB.

AB - This paper presents a Fractional-N (Frac-N) digital phase-locked loop (DPLL) that resolves phase error (PE) in fully differential voltage (FDV) domain, where power-efficient PE detection can be accomplished with higher CMRR, lower PVT sensitivity, finer resolution and better linearity as compared to gate delay-dependent time domain. The implemented DPLL covers the frac-N operation by a 10b DAC in voltage domain (V-domain). A differential dv/dt ramp is employed to linearly transfer the frac-N phase difference into a small range voltage error, which is digitized by a narrow range but fine resolution 7b ADC. The DPLL achieves an integrated RMS jitter of 101fs with -56dBc worst-case fractional spur and consumes 9.2mW which translates to a FoM of -250.3dB.

UR - https://www.scopus.com/pages/publications/85090244420

U2 - 10.1109/VLSICircuits18222.2020.9162777

DO - 10.1109/VLSICircuits18222.2020.9162777

M3 - 会议稿件

AN - SCOPUS:85090244420

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

BT - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020

Y2 - 16 June 2020 through 19 June 2020

ER -

Wu L, Burger T, Schonle P, Huang Q. A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9162777. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSICircuits18222.2020.9162777

A 3.3-GHz 101fsrms-Jitter, -250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain

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