A 24-kHz bandwidth 94.8-dB-SNDR discrete-time dynamic zoom ADC with analog-domain combine

This article presents a discrete-time (DT) dynamic zoom ADC with analog-domain combine and fractional over-ranging factor. The output of the successive approximation register (SAR) ADC and the delta-sigma modulator (DSM) are directly combined by charge transfer through the proposed extended-CDAC, without a digital combine module. It effectively simplifies the digital circuits of the proposed zoom ADC, and saves the area and power consumption. Combining in the analog-domain also makes it possible to adopt a fractional over-ranging factor (M < 1), thus reducing the SQNR loss. Fabricated in a 65-nm CMOS process, the prototype ADC occupies only 0.15 mm² core area and achieves 94.8-dB peak SNDR, 96.7-dB DR in 24-kHz bandwidth, while consuming 178.1-μW from a 1.1-V Supply, leading to an SNDR-based FoM_S of 176.1-dB.