10μW/cm2-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology

M. Tomita; S. Oba; Y. Himeda; R. Yamato; K. Shima; T. Kumada; M. Xu; H. Takezawa; K. Mesaki; K. Tsuda; S. Hashimoto; T. Zhan; H. Zhang; Y. Kamakura; Y. Suzuki; H. Inokawa; H. Ikeda; T. Matsukawa; T. Matsuki; T. Watanabe

doi:10.1109/VLSIT.2018.8510659

10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology

M. Tomita
, S. Oba
, Y. Himeda
, R. Yamato
, K. Shima
, T. Kumada
, M. Xu
, H. Takezawa
, K. Mesaki
, K. Tsuda
, S. Hashimoto
, T. Zhan
, H. Zhang
, Y. Kamakura
, Y. Suzuki
, H. Inokawa
, H. Ikeda
, T. Matsukawa
, T. Matsuki
, T. Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm², which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	93-94
Number of pages	2
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510659
State	Published - 25 Oct 2018
Externally published	Yes
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2018-June
ISSN (Print)	0743-1562

Conference

Conference	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

Access to Document

10.1109/VLSIT.2018.8510659

Cite this

Tomita, M., Oba, S., Himeda, Y., Yamato, R., Shima, K., Kumada, T., Xu, M., Takezawa, H., Mesaki, K., Tsuda, K., Hashimoto, S., Zhan, T., Zhang, H., Kamakura, Y., Suzuki, Y., Inokawa, H., Ikeda, H., Matsukawa, T., Matsuki, T., & Watanabe, T. (2018). 10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 93-94). Article 8510659 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510659

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abstract = "A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.",

author = "M. Tomita and S. Oba and Y. Himeda and R. Yamato and K. Shima and T. Kumada and M. Xu and H. Takezawa and K. Mesaki and K. Tsuda and S. Hashimoto and T. Zhan and H. Zhang and Y. Kamakura and Y. Suzuki and H. Inokawa and H. Ikeda and T. Matsukawa and T. Matsuki and T. Watanabe",

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year = "2018",

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doi = "10.1109/VLSIT.2018.8510659",

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Tomita, M, Oba, S, Himeda, Y, Yamato, R, Shima, K, Kumada, T, Xu, M, Takezawa, H, Mesaki, K, Tsuda, K, Hashimoto, S, Zhan, T, Zhang, H, Kamakura, Y, Suzuki, Y, Inokawa, H, Ikeda, H, Matsukawa, T, Matsuki, T & Watanabe, T 2018, 10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510659, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 93-94, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510659

10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. / Tomita, M.; Oba, S.; Himeda, Y. et al.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 93-94 8510659 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Shima, K.

AU - Kumada, T.

AU - Xu, M.

AU - Takezawa, H.

AU - Mesaki, K.

AU - Tsuda, K.

AU - Hashimoto, S.

AU - Zhan, T.

AU - Zhang, H.

AU - Kamakura, Y.

AU - Suzuki, Y.

AU - Inokawa, H.

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AU - Matsukawa, T.

AU - Matsuki, T.

AU - Watanabe, T.

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AB - A best benchmark of Si-nanowire (NW) thermoelectric (TE) power generator has been achieved by our proposed planar device architecture compatible with CMOS process technology. The TE power density corresponds to 12 μW/cm2, which is recorded at an externally applied temperature difference of only 5 K. The demonstration opens up a pathway to cost effective autonomous internet of things (IoT) application utilizing environmental and body heats.

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Tomita M, Oba S, Himeda Y, Yamato R, Shima K, Kumada T et al. 10μW/cm²-class high power density planar Si-nanowire thermoelectric energy harvester compatible with CMOS-VLSI technology. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 93-94. 8510659. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2018.8510659