自旋轨道力矩磁性随机存储器制造工艺研究

Spin orbit torque magnetic random access memory (SOT-MRAM) represents a next-generation spintronic memory technology, evolving from the field-switched Toggle-MRAM and spin transfer torque (STT) MRAM. Its cell device shows an intrinsic switching speed of up to the sub-nanosecond level, meanwhile the separated read/write path provides higher reliability and greater design flexibility, making it an ideal candidate for constructing non-volatile high-speed cache (L1‒L3 Cache). However, SOT-MRAM remains in the research and development phase, with only a few test chips released, and a series of hurdles need to be addressed before achieving mass production. Especially in terms of manufacturing processes, the ultra-thin SOT channel layer, the top-pinned tunnel junction film stack with dozens of layers of materials, and the hybrid integration between CMOS process and magnetic special process, etc., pose significant challenges to the wafer-level manufacturing of SOT-MRAM. This article focuses on comprehensively elaborating the wafer-level manufacturing process of SOT-MRAM, examining the key issues and challenges related to material systems, film stack etching, and hybrid integration.